MAN1026-02-EN Page 1 of 3 June 9, 2015 © Horner APG LLC. This drawing is the property of Horner APG LLC and shall not be disclosed or reproduced except as specifically authorised. X-Series 106 I/O Board Datasheet 1. Hardware Specification Digital DC Inputs Digital DC Outputs Inputs per Module 12 Outputs per Module 12 Commons per Module 1 Commons per Module 1 Input Voltage Range 0 VDC - 24 VDC Output Type Sourcing / 10 K Pull-Down Absolute Max. Voltage 35 VDC Max. Absolute Max. Voltage 30 VDC Max. Input Impedance 10 k Output Protection Short Circuit & Overvoltage Input Current Minimum ‘On’ current Maximum ‘Off’ current. Positive Logic 0.8 mA 0.3 mA Negative Logic -1.6 mA -2.1 mA Max. Output Current per point 0.5 A Max. Total Current per driver (Q1-4, Q5-8, Q9-12). 2A Continuous Min ‘On’ Input 8 VDC Max. Output Supply Voltage 30 VDC Max ‘Off’ Input 3 VDC Minimum Output Supply Voltage 10 VDC OFF to ON Response 1 ms Max. Voltage Drop at Rated Current 0.25 VDC ON to OFF Response 1 ms Min. Load None Galvanic Isolation None. I/O Indication None Logic Polarity Positive and Negative based on Common pin level. Galvanic Isolation None I/O Indication None. OFF to ON Response 150nS High Speed Counter Inputs* 4 - DIN 8-12 ON to OFF Response 150nS High Speed Counter Max Freq* XLE/T/6/10 / XL4/7 10KHz / 500KHz PWM Out* XLE/T/6/10 / XL4/7 65KHz / 500KHz Connector Type 3.5mm Pluggable cage clamp connector Output Characteristics Current Sourcing (Pos logic) Analog Inputs Number of Channels 6 Absolute max Input Voltage -0.5 -12V dc. (+/-30Vdc) Input Range 0–20mA, 4-20 mA dc. 0-60mV, 0-10V dc. T/C - J, K, N, T, E, R, S, B RTD - PT100, PT1000 Input Impedance (Clamped @ -0.5 to 10.23VDC). T/C / RTD / mV > 2 MΩ mA: 15 Ω + 1.5 V V: 1.1 MΩ Nominal Resolution 14 - 17 Bits (variable depending on input type) Galvanic Isolation None Sensor Range and Accuracy Input Type Range Accuracy TC J -120 to 1000°C / -184 to 1832°F ± 0.2% FS ± 1°C TC K -130 to 1372°C / -202 to 2501.6°F ± 0.2% FS ± 1°C TC T -130 to 400°C / -202 to 752°F ± 0.2% FS ± 1°C TC E -130 to 780°C / -202 to 1436°F ± 0.2% FS ± 1°C TC N -130 to 1300°C / -202 to 2372°F ± 0.2% FS ± 1°C TC R, S 20 to 1768°C / 68 to 3214.4°F ± 0.2% FS ± 3°C TC B 100 to 1820°C / 212 to 3308°F ± 0.2% FS ± 3°C PT100/1000 -200 to 850°C / -328 to 1562°F ± 0.15% FS 0-20mA 0-20mA ± 0.15% FS 0-60mV 0-60mV ± 0.15% FS 0-10V 0-10V ± 0.15% FS Conversion Speed Minimum all channels converted in approx. 150mS. Analogue Outputs Analog Outputs Number of Channels 4 Minimum Current load 500Ω Output Ranges 0 – 10Vdc. 0 – 20mA, 4-20mA dc Galvanic Isolation None Nominal Resolution 12 Bits Conversion Speed Min all channels once per scan. Response Time One update per ladder scan. Max. Error at 25C (excluding zero) 0-20 mA 0.1% of full scale. 0-10 V 0.1% of full scale Additional Error for temperatures other than 25C 20mA 0.0126%/°C. *see I/O information below for detail regarding HSC and PWM MAN1026-02-EN Page 2 of 3 June 9, 2015 © Horner APG LLC. This drawing is the property of Horner APG LLC and shall not be disclosed or reproduced except as specifically authorised. (Black/ Green) Signal Name 2A V3 V OUT 3* V2 V OUT 2* V1 V OUT 1* mA4 mA Out 4* mA3 mA Out 3* mA2 mA Out 2* mA1 mA Out 1* Q1 OUT 1 / PWM1 Q2 OUT 2 / PWM2 2B Q3 OUT 3 Q4 OUT 4 Q5 OUT 5 Q6 OUT 6 Q7 OUT 7 Q8 OUT 8 Q9 OUT 9 Q10 OUT 10 Q11 OUT 11 Q12 OUT 12 V+ V External+ 0V Common 2. Connection Details 2.2 Example Universal Input Wiring Schematic J1 (Orange/ Green) Signal Name J1A I1 V IN1 I2 V IN2 I3 V IN3 I4 V IN4 I5 V IN5 I6 V IN6 I7 V IN7 I8 V IN8 H1 HSC1 / V IN9 H2 HSC2 / V IN10 H3 HSC3 / V IN11 H4 HSC4 / V IN12 J1B 0V Common A1A Univ. AI 1 pin 1 A1B Univ. AI 1 pin 2 A1C Univ. AI 1 pin 3 N/C No Connection A2A Univ. AI 2 pin 1 A2B Univ. AI 2 pin 2 A2C Univ. AI 2 pin 3 N/C No Connection J3 (Orange/ Green) Signal Name Univ. AI N/C No Connection A3A Univ. AI 3 pin 1 A3B Univ. AI 3 pin 2 A3C Univ. AI 3 pin 3 N/C No Connection A4A Univ. AI 4 pin 1 A4B Univ. AI 4 pin 2 A4C Univ. AI 4 pin 3 N/C No Connection Univ. AI A5A Univ. AI 5 pin 1 A5B Univ. AI 5 pin 2 A5C Univ. AI 5 pin 3 N/C No Connection A6A Univ. AI 6 pin 1 A6B Univ. AI 6 pin 2 A6C Univ. AI 6 pin 3 0V Common V4 V OUT4* Note * Both mA & V outputs are active for each output channel, however, only the configured output type is calibrated (maximum 4 channels simultaneously). For ease of operability, the high density terminals are divided into more manageable pairs of connectors (J1A + J1B, J2A + J2B, J3A + J3B) To ensure proper installation, connector symbols must match as seen below: MAN1026-02-EN Page 3 of 3 June 9, 2015 © Horner APG LLC. This drawing is the property of Horner APG LLC and shall not be disclosed or reproduced except as specifically authorised. 3. Configuration The data registers are as follows: Digital Inputs Digital Outputs Analogue Inputs Analogue Outputs %I1-12 %Q1-12 %AI1-4, %AI33-38 %AQ9-12 Note that the first four analogue inputs are mapped to both %AI1-4 and %AI33-36, analogue input channels 5 & 6 are mapped to %AI37 and %AI38 respectively only. 3.1 Data values: The analogue inputs return data types as follows: Input Mode Data format Comment 0-2mA, 4-20mA 0-32000 0-10V, 0-60mV 0-32000 T/C, RTD Temperature in °C or °F to 1 decimal place xxx.y °C or °F may be selected in the I/O config section. The value is an integer, the user should divide by 10. 3.2 Status Register Register Description %R1 Bit-wise status register enable – R1.1 – R1.9 enable for registers R2 to R9 %R2 Firmware version %R3 Watchdog count – cleared on power-up. %R4 Status bits - 16…4 3 2 1 Reserved Normal Config Calibration %R5 Scan rate of the 106 board (average) in units of 100µS. %R6 Scan rate of the 106 board (max) in units of 100µS. %R7 Channel Status Channel 2 Channel 1 8 7 6 5 4 3 2 1 Open RTD Out of Limits Shorted RTD Open T/C Open RTD Out of Limits Shorted RTD Open T/C %R8 Channel Status Channel 4 Channel 3 8 7 6 5 4 3 2 1 Open RTD Out of Limits Shorted RTD Open T/C Open RTD Out of Limits Shorted RTD Open T/C %R9 Channel Status Channel 6 Channel 5 8 7 6 5 4 3 2 1 Open RTD Out of Limits Shorted RTD Open T/C Open RTD Out of Limits Shorted RTD Open T/C %R10-14 Reserved Note: For the purposes of the example, the block is shown starting at %R1, but it can be set to anywhere in the %R memory map.